1. Field of the Invention
The present invention relates to a solid-state image pickup device, a method of manufacturing thereof, and an electronic apparatus applied to a camera or the like provided with the solid-state image pickup device.
2. Description of the Related Art
As a solid-state image pickup device (image sensor), a CMOS (Complementary Metal Oxide Semiconductor) solid-state image pickup device is known. Since the CMOS solid-state image pickup device is driven with low voltage and low power consumption, the CMOS solid-state image pickup device is used for digital still cameras, digital video cameras, various mobile terminals such as mobile phones attached with a camera, or the like.
Each pixel in the CMOS solid-state image pickup device includes a photodiode as a photoelectric conversion portion receiving light and a plurality of pixel transistors outputting signals. In general, output signals are accumulated in an impurity diffusion layer, which is referred to as a floating diffusion (FD), in a silicon substrate and amplified by an amplifying transistor to be output.
Recently, as a technology of widening the dynamic range of the image sensor, disclosed is a technology where, besides the floating diffusion (FD), capacitance elements are formed in the substrate, and charges are also accumulated in the capacitance elements. This technology is disclosed in Japanese Journal of Applied Physics, vol. 47, No. 7, pp. 5390-5395, (2008) and Technical Digest of VLSI Circuit Technology, pp. 180-181, (2009), where a photodiode, a plurality of pixel transistors outputting signals, and a capacitance element for charge accumulation are included in each pixel.
FIG. 18 illustrates a layout of a pixel provided with a capacitance element disclosed in Technical Digest of VLSI Circuit Technology, pp. 180-181, (2009). In this CMOS solid-state image pickup device, a photodiode PD and a plurality of pixel transistors, that is, a transfer transistor Tr1, a reset transistor Tr2, an amplifying transistor Tr3, a column selecting transistor Tr4, and a capacitance selecting transistor Tr5 are formed in one pixel 111. T denotes a transfer gate electrode, FD denotes a floating diffusion, S denotes a capacitance selecting gate electrode, R denotes a reset gate electrode, SF denotes an amplifying gate electrode, and X denotes a column selecting gate electrode. In addition, a capacitance element 112 for charge accumulation is formed in the pixel 111. The one end of the capacitance element 112 is connected to a common source/drain region 113 of the reset transistor Tr2 and the capacitance selecting transistor Tr5, and the other end thereof is connected to a ground or a power supply VDD. A vertical signal line (not shown) is connected to a source/drain region 114 of the one side of the column selecting transistor Tr4.
In addition, on the other hand, a back side illuminated type CMOS solid-state image pickup device where wire lines are formed on a front surface side of a semiconductor substrate for implementation of high sensitivity in a CMOS solid-state image pickup device and image capturing is performed by using light which is incident from a rear surface side of the semiconductor substrate is disclosed in, for example, Japanese Patent No. 4123415, Japanese Unexamined Patent Application Publication Nos. 2003-31785 and 2006-245499. In the case of the back side illuminated type CMOS solid-state image pickup device, as illustrated in FIG. 4 of Japanese Patent No. 4123415, the wire line layer in the front surface of the semiconductor substrate may be disposed just above the photodiode without consideration of the light incident to the photodiode.
In addition, recently, a module where a CMOS solid-state image pickup device chip and a logic LSI chip are three-dimensionally laminated is disclosed in Japanese Unexamined Patent Application Publication Nos. 2002-44527 and 2006-49361, and the like. In this technology, the solid-state image pickup device chip is laminated on a chip, on which an AD converter or a memory is mounted, by using bump connection, so that miniaturization is implemented.
FIG. 19 illustrates a CMOS solid-state image pickup device 115 where a first semiconductor chip 116 including an image pickup area on which a plurality of pixels are arrayed in a two-dimensional array shape and a second semiconductor chip 117 on which logic circuits are formed are laminated. In the second semiconductor chip 117, a memory 118, an analog digital converter (hereinafter, referred to as an A/D converter), and the like are formed. In addition, in the second semiconductor chip 117, an area 119 where the first semiconductor chip 116 is to be laminated and other circuits are formed.
In addition, a CMOS solid-state image pickup device where light transmitting through a photoelectric conversion portion is reflected so as to be incident again to the photoelectric conversion portion is also disclosed in Japanese Unexamined Patent Application Publication No. 2008-147333 or the like.